[Libre-soc-bugs] [Bug 382] nmigen wishbone Memory (SRAM) object needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=382

--- Comment #11 from Yehowshua <yimmanuel3 at gatech.edu> ---
In fact, Minerva's cache codebase is really bizarre.
We'd really have to shoe horn it I think.

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