[Libre-soc-bugs] [Bug 382] nmigen wishbone Memory (SRAM) object needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=382

--- Comment #10 from Yehowshua <yimmanuel3 at gatech.edu> ---
You can't write to Minerva's cache.
I was to shy to say this before because it sounds silly and I thought maybe I
didn't understand Minerva.
But after EXTENSIVE review, I'm certain this is the case.
Minerva handles writes by going directly to memory.
In fact, Minerva's Cache is really really simple - I don't think its what we're
looking for.

Luke, I HAVE to have a cache for my thesis, so I'm thinking of writing one.
Maybe I can kill two birds with one stone - just tell me what the cache must be
able to do.
I can also formally verify it no problem.

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