[Libre-soc-bugs] [Bug 382] nmigen wishbone Memory (SRAM) object needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=382

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Yehowshua from comment #9)
> > yehowshua, hi, can you please put where the external source code is that
> > contains
> 
> Just now saw this. Glad you found it!
> Also, what was the bug in SRAM.py?


            n_wrport = wrport.en.shape()[0]
            n_bussel = self.bus.sel.shape()[0]
            assert n_wrport == n_bussel, "bus enable count %d " \
                    "must match memory wen count %d" % (n_wrport, n_bussel)
            for i in range(n_wrport):
                m.d.comb += wrport.en[i].eq(self.bus.cyc & self.bus.stb &
                                            self.bus.we & self.bus.sel[i])

was:
            for i in range(4):

which would only copy over a subset of wen signals.  and on certain
granularities would overrun the wen array.

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