[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #138 from Samuel A. Falvo II <kc5tja at arrl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #137)
>                  # check EE (48) IR (58), DR (59): PR (49) will over-ride
> -                comb += [
> -                    Assert(msr_o[48] == (srr1_i[48] | srr1_i[48])), # EE
> -                    Assert(msr_o[58] == (srr1_i[58] | srr1_i[58])), # IR
> -                    Assert(msr_o[59] == (srr1_i[59] | srr1_i[59])), # DR
> -                ]
> 
> nuts i wrote a nice explanation then lost the browser connection.  can you
> restore these lines because they look like the pseudocode and were carefully
> crafted tgat way.
> 
> expanding the loop is even less clear.

Wouldn't msr_o[48] refer to the LSB-0 bit 48 though?  That seems like it'd pick
the wrong bit to check.

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