[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #137 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
                 # check EE (48) IR (58), DR (59): PR (49) will over-ride
-                comb += [
-                    Assert(msr_o[48] == (srr1_i[48] | srr1_i[48])), # EE
-                    Assert(msr_o[58] == (srr1_i[58] | srr1_i[58])), # IR
-                    Assert(msr_o[59] == (srr1_i[59] | srr1_i[59])), # DR
-                ]

nuts i wrote a nice explanation then lost the browser connection.  can you
restore these lines because they look like the pseudocode and were carefully
crafted tgat way.

expanding the loop is even less clear.

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