[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #123 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
@@ -242,13 +256,6 @@ class TrapMainStage(PipeModBase):
                 # check problem state
                 msr_check_pr(m, msr_o.data)

-                # hypervisor stuff.  here: bits 3 (HV) and 51 (ME) were
-                # copied over by msr_copy but if HV was not set we need
-                # the *original* (msr_i) bits
-                with m.If(~msr_i[MSR.HV]):
-                    comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV])
-                    comb += msr_o.data[MSR.ME].eq(msr_i[MSR.ME])
-
                 # don't understand but it's in the spec.  again: bits 32-34
                 # are copied from srr1_i and need *restoring* to msr_i
                 bits = slice(63-31,63-29+1) # bits 29, 30, 31 (Power notation)


mm removing that does not feel right.  i believe this is what microwatt is
doing and removing what microwatt does is inadviseable.

have to check 1 sec

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