[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #120 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
-                # TODO: check ordering (which is smaller, which is larger)
-                # MSR.TSs or MSR.TSe+1?

+                comb += field(expected_msr, MSRb.TEs, MSRb.TEe).eq(0)


this is still wrong.  the left side of the slice is still greater tham the
right side of the slice because MSR.TEs is less than MSR.TEb which, after
subtraction from 63 become the other way round.

therefore not only does the code do nothing, the Assertion returns an rempty
list on both sides of the "==" which evaluates to TRUE which will always
silently succeed.

-- 
You are receiving this mail because:
You are on the CC list for the bug.