[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #118 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=6e9aab358be8cd5f53494c035f0bc67dd7826b5d

this is in ISACaller.TRAP()

-        self.msr[63-MSR.SF] = 1
-        self.msr[63-MSR.EE] = 0
-        self.msr[63-MSR.PR] = 0
-        self.msr[63-MSR.IR] = 0
-        self.msr[63-MSR.DR] = 0
-        self.msr[63-MSR.RI] = 0
-        self.msr[63-MSR.LE] = 1
+        self.msr[MSRb.SF] = 1
+        self.msr[MSRb.EE] = 0
+        self.msr[MSRb.PR] = 0
+        self.msr[MSRb.IR] = 0
+        self.msr[MSRb.DR] = 0
+        self.msr[MSRb.RI] = 0
+        self.msr[MSRb.LE] = 1

i liked the idea of not doing the (silly) 63-NNN stuff, so changed things
to use explicit class/enums that do the 63- for us.

also i need to update ISACaller.TRAP() to reflect the bitfield changes
in trap main_stage.py (and the proof):

                ...
                ...
                comb += expected_msr[MSR.VSX].eq(0)
                comb += expected_msr[MSR.PR].eq(0)
                comb += expected_msr[MSR.FP].eq(0)
                comb += expected_msr[MSR.PMM].eq(0)

i'll do that now.

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