[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #21)
> Sorry to bother you... Same player shoot again.
> 
> Traceback (most recent call last):
>   File "./test_issuer.py", line 36, in <module>
>     from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
>   File ".../soc/src/soc/simulator/test_sim.py", line 3, in <module>
>     from nmigen.test.utils import FHDLTestCase
> ModuleNotFoundError: No module named 'nmigen.test'

sigh it's likely nmigen.test has been removed (or moved) in the past day
or so. sorted:

commit 4d8a7e65660df9e41a061997631763d51dbe2124 (HEAD -> master, origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Tue Jul 21 15:14:00 2020 +0100

    spurious imports of FHDLTestCase, should be from nmutil


generally, keeping "up-to-date" with absolute latest nmigen is inadviseable
without coordinating: it's a moving target.

-- 
You are receiving this mail because:
You are on the CC list for the bug.