[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #21 from Jean-Paul.Chaput at lip6.fr ---
Sorry to bother you... Same player shoot again.

Traceback (most recent call last):
  File "./test_issuer.py", line 36, in <module>
    from soc.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  File ".../soc/src/soc/simulator/test_sim.py", line 3, in <module>
    from nmigen.test.utils import FHDLTestCase
ModuleNotFoundError: No module named 'nmigen.test'

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