[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=417

--- Comment #17 from Cesar Strauss <cestrauss at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #16)
> cesar: i *removed* the first yield and things still "work" (work in
> both)

Sure. On pysim, because there is an extra ready_i from the previous
transaction, the new transaction begins with a ready_i cycle already in
progress.

It does not change the fact that the extra ready_i at the end of transaction
shouldn't be there, on pysim.

Note that a similar issue happens on the sender side. In cxxsim, due to the
first yield, the sender misses the first ready_o pulse, and keeps the data
valid until the next ready_o.

> i have absolutely no idea which of these is "right".

I vote for pysim being right.

Can we, for the time being, do the following? It seems to work on both pysim
and cxxsim. The waveforms match, within a half clock of delay.

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index b3ab5b17..4237a3fd 100644
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -221,10 +221,15 @@ def test_shifter():
         yield dut.p.data_i.shift.eq(shift)
         yield dut.op.sdir.eq(direction)
         yield dut.p.valid_i.eq(1)
-        yield
+        # TODO: put back this missing yield when cxxsim starts matching pysim
+        if not cxxsim:
+            yield
         # wait for p.ready_o to be asserted
         while not (yield dut.p.ready_o):
             yield
+        # TODO: remove this extra yield when cxxsim starts matching pysim
+        if cxxsim:
+            yield
         # clear input data and negate p.valid_i
         yield dut.p.valid_i.eq(0)
         yield dut.p.data_i.data.eq(0)
@@ -234,15 +239,18 @@ def test_shifter():
     def receive(expected):
         # signal readiness to receive data
         yield dut.n.ready_i.eq(1)
-        yield
+        # TODO: put back this missing yield when cxxsim starts matching pysim
+        if not cxxsim:
+            yield
         # wait for n.valid_o to be asserted
         while not (yield dut.n.valid_o):
             yield
         # read result
         result = yield dut.n.data_o.data

-        # must leave ready_i valid for 1 cycle, ready_i to register for 1
cycle
-        yield
+        # TODO: remove this extra yield when cxxsim starts matching pysim
+        if cxxsim:
+            yield
         # negate n.ready_i
         yield dut.n.ready_i.eq(0)
         # check result

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