[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=417

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
cesar: i *removed* the first yield and things still "work" (work in
both)

        # signal readiness to receive data
        yield dut.n.ready_i.eq(1)
        # yield REMOVED HERE

        # wait for n.valid_o to be asserted
        valid_o = yield dut.n.valid_o
        print ("        valid_o", valid_o)
        while not (yield dut.n.valid_o):
            valid_o = yield dut.n.valid_o
            print ("        valid_o", valid_o)
            yield

        # read result
        result = yield dut.n.data_o.data

        # "FIX" the problem with this line:
        yield    # <---- remove this - pysim "works" but cxxsim does not

in other words, the ready is asserted and testing of valid is done
immediately (in the same cycle).  however valid_o is held for one
cycle *after*.

i have absolutely no idea which of these is "right".

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