[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=469

--- Comment #16 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
        index    = Signal(log2_int(TLB_SET_BITS), False)
        addrbits = Signal(TLB_SET_BITS)

        amin = TLB_LG_PGSZ
        amax = TLB_LG_PGSZ + TLB_SET_BITS

        with m.If(m_in.valid):
            comb += addrbits.eq(m_in.addr[amin : amax])
        with m.Else():
            comb += addrbits.eq(d_in.addr[amin : amax])
        comb += index.eq(addrbits)

        #             if r0_stall = '0' then
        # If we have any op and the previous op isn't finished,
        # then keep the same output for next cycle.
        with m.If(~r0_stall):
            sync += tlb_valid_way.eq(dtlb_valid_bits[index])
            sync += tlb_tag_way.eq(dtlb_tags[index])
            sync += tlb_pte_way.eq(dtlb_ptes[index])

previously, you had sync += addrbits and sync += index.

what this would do is:

* on the first clock cycle, m_in.valid would be tested
* on the second cycle, a value of addrbits would be valid
* on the third cycle, the value of addrbits would become valid in index
* on the fourth cycle, the test of r0_stall would finally result in
  tlb_*_way being updated...

... with values that were far, far too late.

if you look at the original dcache.vhdl you will see that index and addrbits
were "variables", not signals.  this is a sign that needs to be looked out for.

-- 
You are receiving this mail because:
You are on the CC list for the bug.