[Libre-soc-bugs] [Bug 469] Create D-cache from microwatt dcache.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=469

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
cole, only comb += defaults to equal-to-the-reset.

for sync the value is stored in a latch and so if it is not set it will
*remain* at the (incorrect) value.


    #                 r.req := d_in;
    #                 r.tlbie := '0';
    #                 r.doall := '0';
    #                 r.tlbld := '0';
    #                 r.mmu_req := '0';
                sync += r.req.eq(d_in)
                sync += r.req.tlbie.eq(0)
                sync += r.req.doall.eq(0)
                sync += r.req.tlbd.eq(0)
                sync += r.req.mmu_req.eq(0)

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