[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #18 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Cole Poirier from comment #16)
> (In reply to Luke Kenneth Casson Leighton from comment #14)
> > note how the git diff wraps?  did you remember to do "git diff" before each
> > commit?
> > 
> > 
> > diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
> > index e4779962..d5cba5a2 100644
> > --- a/src/soc/experiment/mmu.py
> > +++ b/src/soc/experiment/mmu.py
> > @@ -572,7 +572,7 @@ class AddrShifter(Elaboratable):
> >  #           -- rts == radix tree size, # address bits being translated
> >  #           rts := unsigned('0' & pgtbl(62 downto 61) & pgtbl(7 downto 5));
> >              # rts == radix tree size, number of address bits being
> > translated
> > -            comb += rts.eq(((Cat(Const(0b0, 1) , Cat(pgtbl[61:63],
> > pgtbl[5:8]))).as_unsigned())
> > +            comb += rts.eq((0 & pgtbl[61:63] & pgtbl[5:8]).as_unsigned())
> >  
> >  #           -- mbits == # address bits to index top level of tree
> >  #           mbits := unsigned('0' & pgtbl(4 downto 0));
> 
> Oops sorry about that! Will fix now.

Hold on... Isn't that git diff showing me fixing formatting that wrapped? Cause
that's what it looks like now that I'm taking a second closer look. Can you
clarify?

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