[Libre-soc-bugs] [Bug 450] Create MMU from microwatt mmu.vhdl

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=450

--- Comment #17 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #15)
> (In reply to Cole Poirier from comment #13)
> > (In reply to Luke Kenneth Casson Leighton from comment #12)
> > > btw do these modifications *one at a time*, committing them with a link to
> > > the relevant comment.
> > > 
> > > *DO NOT* do all of them in one single massive commit.
> > 
> > Thanks for all the help! Did an individual commit per comment for most of
> > them, combined two comments into one commit where it made sense, i.e. the
> > deletions at the top of what was formerly MMU0(process)
> 
> sense to whom? :)
> 
> now i cannot review and confirm each commit.... because they're merged.
> 
> how can i tell that this does what is needed, by looking at it?
> 
> can you tell, easily and at a glance, which lines were deleted and which
> were indented?

Yes, but that's only because I *just* did it. Sorry, should have followed your
directions to the letter. I being far less experience in git than you didn't
realize the indentation would show up as additions. So, yes should have
followed to the letter, given that you foresaw this negative consequence.

> diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
> index 083b2b66..e4779962 100644
> --- a/src/soc/experiment/mmu.py
> +++ b/src/soc/experiment/mmu.py
> @@ -176,47 +176,83 @@ class MMU(Elaboratable):
>          with m.Else():
>              comb += l_out.sprval.eq(0x00000000 & r)
>  
> -#       if rin.valid = '1' then
> -#           report "MMU got tlb miss for " & to_hstring(rin.addr);
> -#       end if;
> -        with m.If(rin.valid == 1):
> -            print(f"MMU got tlb miss for {rin.addr}")
>  
> -#       if l_out.done = '1' then
> -#           report "MMU completing op without error";
> -#       end if;
> -        with m.If(l_out.done == 1):
> -            print("MMU completing op without error")
>  
> -#       if l_out.err = '1' then
> -#           report "MMU completing op with err invalid=" &
> +# mmu_0: process(clk)
> +class MMU0(Elaboratable):
> +    def __init__(self, clk):
> +        self.clk = clk
> +
> +# begin
> +    def elaborate(self, platform):
> +
> +        m = Module()
> +
> +        comb = m.d.comb
> +        sync = m.d.sync
> +
> +        rst = ResetSignal()
> +
> +#       if rising_edge(clk) then
> +        with m.If(rising_edge):
> +#           if rst = '1' then
> +            with m.If(rst == 1):
> +#               r.state <= IDLE;
> +#               r.valid <= '0';
> +#               r.pt0_valid <= '0';
> +#               r.pt3_valid <= '0';
> +#               r.prtbl <= (others => '0');
> +                sync += r.state.eq(State.IDLE)
> +                sync += r.valid.eq(0)
> +                sync += r.pt0_valid.eq(0)
> +                sync += r.pt3_valid.eq(0)
> +                # TODO value should be vhdl (others => '0') in nmigen
> +                sync += r.prtbl.eq(0)
> +#           else
> +            with m.Else():
> +#               if rin.valid = '1' then
> +#                   report "MMU got tlb miss for " & to_hstring(rin.addr);
> +#               end if;
> +                with m.If(rin.valid == 1):
> +                    print(f"MMU got tlb miss for {rin.addr}")
> +
> +#               if l_out.done = '1' then
> +#                   report "MMU completing op without error";
> +#               end if;
> +                with m.If(l_out.done == 1):
> +                    print("MMU completing op without error")
> +
> +#               if l_out.err = '1' then
> +#                   report "MMU completing op with err invalid=" &
>  #                   std_ulogic'image(l_out.invalid) & " badtree=" &

-- 
You are receiving this mail because:
You are on the CC list for the bug.