[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #71 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #70)
> and, really, i wanted the "skip if there are 8 bytes of zeros"
> capability that's in microwatt's divide.vhdl FSM.  which can be
> done as an enhancement under a separate bugreport, given that
> it's strictly speaking an optimisation.

if I'm going to spend any time optimizing, I think it would be better spent
converting the FSM to a radix 4 or 8 divider and/or adding support for skipping
ahead by using find-first-set-bit on both remainder and divisor to skip runs of
zeros. increasing the radix would multiply the area to several
adders/subtractors instead of one. adding the run-skipping would require 2 find
first set bit circuits and a 128-bit variable shifter for dividend_quotient,
which I think might be a bit too much unless we limit the max shift amount to 7
bits or so.

> remember to track it on your libre-soc homepage, cut/paste from
> here https://libre-soc.org/lkcl

already done.

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