[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=324

--- Comment #70 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #69)
> As of soc.git commit 837d9fbdd54265a63a07e475b6d85313cadf2927, all tests
> pass, so I declare this complete.

it's a leeettle premature: test_issuer.py needed to be run with the
DivTestCases

commit b6223dc2bd7125b6d12a5cd8a220fa76ca124549 (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed Aug 5 12:32:45 2020 +0100

    add div test cases into test_issuer.py


checking that it compiles in coriolis2 needed to be done (it does)

commit 4cb01cbff73a8e5cf74282f260be6a9a1f666b00 (origin/master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Wed Aug 5 10:29:44 2020 +0100

    add div FSM as default for test_issuer in verilog and ilang gen


and the verilog simulation checked (still TODO)

and, really, i wanted the "skip if there are 8 bytes of zeros"
capability that's in microwatt's divide.vhdl FSM.  which can be
done as an enhancement under a separate bugreport, given that
it's strictly speaking an optimisation.

apaaart from all that... yes :)

remember to track it on your libre-soc homepage, cut/paste from
here https://libre-soc.org/lkcl

-- 
You are receiving this mail because:
You are on the CC list for the bug.