[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline
bugzilla-daemon at libre-soc.org
bugzilla-daemon at libre-soc.org
Wed Aug 5 23:34:22 BST 2020
https://bugs.libre-soc.org/show_bug.cgi?id=324
--- Comment #72 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #71)
> (In reply to Luke Kenneth Casson Leighton from comment #70)
> > and, really, i wanted the "skip if there are 8 bytes of zeros"
> > capability that's in microwatt's divide.vhdl FSM. which can be
> > done as an enhancement under a separate bugreport, given that
> > it's strictly speaking an optimisation.
>
> if I'm going to spend any time optimizing, I think it would be better spent
> converting the FSM to a radix 4 or 8 divider and/or adding support for
> skipping ahead by using find-first-set-bit on both remainder and divisor to
> skip runs of zeros.
that's an interesting idea. microwatt just tests "is the next 8 bits of q ==
0" if so skip 16 bits.
that is a fixed shift amount, so is particularly efficient.
let's raise a new bugreport and discuss it there.
> increasing the radix would multiply the area to several
> adders/subtractors instead of one. adding the run-skipping would require 2
> find first set bit circuits and a 128-bit variable shifter for
> dividend_quotient, which I think might be a bit too much unless we limit the
> max shift amount to 7 bits or so.
well, you'll find this hilarious: currently, the div FSM is so small that it is
difficult to compute a block in coriolis2 which will take the inputs and
outputs on one side.
we actually *need* it to be bigger :)
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