[Libre-soc-bugs] [Bug 373] Investigate the possibility of implementing parts of OPENCAPI to supplement Wisbone vB4

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=373

--- Comment #6 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Cole Poirier from comment #5)
> (In reply to Jacob Lifshay from comment #3)
> > (In reply to Luke Kenneth Casson Leighton from comment #2)
> > > 25ghz external clock requires an internal 50 ghz stable PLL, which is 14nm
> > > territory.
> > 
> > I don't think that's actually true, all you need is a 25GHz PLL with a
> > approx. 50% duty cycle and to use both negative and positive edge-triggered
> > flip flops.
> 
> Ok so "Not possible until after 28nm quadcore asic due to 25GHz clock
> requirement." is accurate right?

I'm not sure, it's probably possible due to only needing 25GHz signalling right
at the I/O circuit, using 12.5GHz or slower everywhere else, but may be lots of
effort due to the unusual design required.

> And this should remain a deferred bug
> report? Or should it be closed entirely?

We can definitely use part of OpenCAPI's logical protocol without actually
needing 25GHz signalling, so maybe defer till after the oct 2020 tapeout?
definitely should not be closed based on 25GHz.

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