[Libre-soc-bugs] [Bug 373] Investigate the possibility of implementing parts of OPENCAPI to supplement Wisbone vB4

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=373

--- Comment #7 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Jacob Lifshay from comment #6)
> I'm not sure, it's probably possible due to only needing 25GHz signalling
> right at the I/O circuit, using 12.5GHz or slower everywhere else, but may
> be lots of effort due to the unusual design required.
> 
> > And this should remain a deferred bug
> > report? Or should it be closed entirely?
> 
> We can definitely use part of OpenCAPI's logical protocol without actually
> needing 25GHz signalling, so maybe defer till after the oct 2020 tapeout?
> definitely should not be closed based on 25GHz.

Cool! That's exactly what I was wondering about when I created this! :)

Happy to hear that we can likely use the some part of the logical protocol
before reaching 12.5GHz external PLLs.

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