[Libre-soc-bugs] [Bug 373] Investigate the possibility of implementing parts of OPENCAPI to supplement Wisbone vB4

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=373

--- Comment #5 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Jacob Lifshay from comment #3)
> (In reply to Luke Kenneth Casson Leighton from comment #2)
> > 25ghz external clock requires an internal 50 ghz stable PLL, which is 14nm
> > territory.
> 
> I don't think that's actually true, all you need is a 25GHz PLL with a
> approx. 50% duty cycle and to use both negative and positive edge-triggered
> flip flops.

Ok so "Not possible until after 28nm quadcore asic due to 25GHz clock
requirement." is accurate right? And this should remain a deferred bug report?
Or should it be closed entirely?

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