[Libre-soc-dev] ddr3 on orangecrab & wishbone clock domain crossing

[Jacob Lifshay]

iirc luke tried using the ddr3 on the orangecrab 85f (which is waay better
than hyperram if we can get it to work, since we have 512MiB rather than
the hyperram sizes of 8MiB or 32MiB) but libre-soc and microwatt were too
slow to init it...a good solution is to have the ddr3 interface on a
separate clock domain that can run as fast as needed, and use a wishbone
clock domain crossing module between the cpu/cache/etc. and the litedram
interface.

some cursory googling gave me:
https://github.com/alexforencich/verilog-wishbone#wb_async_reg-module

Jacob