[Libre-soc-dev] ddr3 on orangecrab & wishbone clock domain crossing

[Luke Kenneth Casson Leighton]

On Thu, Mar 17, 2022 at 9:55 PM Jacob Lifshay <programmerjake at gmail.com> wrote:

> some cursory googling gave me:
> https://github.com/alexforencich/verilog-wishbone#wb_async_reg-module

ah brilliant, i was just thinking along those lines.  i'd started on putting in
nmigen ASyncFIFOs into the DDR wishbone-to-DDR3-command-queue
but shelved it.

l.