[Libre-soc-dev] Fwd: Re: NGI POINTER gigabit ethernet router ASIC roadmap

lkcl luke.leighton at gmail.com
Mon Nov 1 15:12:31 GMT 2021

-------- Original Message --------
From: lkcl <luke.leighton at gmail.com>
Sent: November 1, 2021 2:50:01 PM UTC
To: Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
Subject: Re: NGI POINTER gigabit ethernet router ASIC roadmap

On November 1, 2021 2:03:14 PM UTC, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> wrote:

>> i realise that is a hell of a lot of clock trees :)
>Question is: do those clocks needed to be distributed across all the

no, not at all.  if the PHY is kept very close to the pins it is extremely localised.  i am guessing perhaps only 2000 gates maximum. very tiny.

>or only over certain area? Put another way, are they connected to
>sub-blocks so we can restrict their placement (likely candidates
>  and usb_clk).

definitely sub-blocks, and there will (just like in JTAG) be asynchronous transfer to the sys_clk domain (CDC).

btw JTAG could in theory be done the same, but the sub-block is a bit bigger, it has a Wishbone Memory interface, DMI interface, etc.

the only thing there being, the Boundary Scan Registers are set under JTAG_TCK but the Muxes themselves are Combinatorial after that.  so in *theory* even the Boundary Scan Registers could be within the sub-block and a series of combinatorial selector wires out to the MUXes between IO Pads and Core IO distributes out widely without needing JTAG_TCK to also go with it.

have to check again, but JTAG could be... of the order of... 5000 gates? quite a lot of DFF Registers (over 128 IO pins, because 5x RGMII @ 20 pins each)

>> also, very important: the USB3300 *must* supply its own 1.8v VREF for
>the Digital
>> IO.  i realise that this means 3 Power Rails.  if that is a problem
>then we find a
>> different PHY *or* on the PCB have a Level-Shifter IO IC, 60 mhz is
>not difficult to
>> do.
>I think this is more a question for Staf first. The power routing
>inside the
>  I/O pad is mainly defined by the I/O pad cells layout.

Staf I remember explained to you and me that the ESD issues are easily solved if you only have 2 POWER domains, all GPIO on one ring, all CPU on another.

when there are two or more GPIO rings he said it gets complicated to protect everything from ESD.

in the interests of expediency and to not give ourselves more hell than is strictly necessary i have absolutely no problem at all keeping to only the 2 POWER domains again.

a Level Shifter or four, is perfectly fine:


this is a bi-directional push-pull 6-bit shifter, which can have two completely different voltages from 1.0-5.5v on one side and 1.4-5.5v on the other.

i have used it successfully for Micro-SD conversion from 1.8v to 3.3v at 50 mhz in the past.


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