[Libre-soc-dev] Fwd: Re: NGI POINTER gigabit ethernet router ASIC roadmap

lkcl luke.leighton at gmail.com
Mon Nov 1 14:51:19 GMT 2021

-------- Original Message --------
From: Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
Sent: November 1, 2021 2:03:14 PM UTC
To: lkcl <luke.leighton at gmail.com>
Subject: Re: NGI POINTER gigabit ethernet router ASIC roadmap

On Mon, 2021-11-01 at 13:43 +0000, lkcl wrote:
> in both cases it is the *PHY* that generates the incoming clock used by the ASIC,
> pretty much exactly as is the case with JTAG, in fact the exact same techniques as c4m-
> jtag HDL can be used: to drive the ASIC PHY by the incoming clock, on both rising and
> falling edge, for both Tx and Rx.
> this does mean however we will have:
> * main pll_clk going to PLL to generate sys_clk
> * jtag_tck (25 khz max)
> * eth_clk (125 mhz max)  there will be FIVE of these
> * usb_clk (60 mhz max)    there will be TWO of these
> i realise that is a hell of a lot of clock trees :)

  Question is: do those clocks needed to be distributed across all the design
  or only over certain area? Put another way, are they connected to specific
  sub-blocks so we can restrict their placement (likely candidates eth_clk
  and usb_clk).

> also, very important: the USB3300 *must* supply its own 1.8v VREF for the Digital
> IO.  i realise that this means 3 Power Rails.  if that is a problem then we find a
> different PHY *or* on the PCB have a Level-Shifter IO IC, 60 mhz is not difficult to
> do.

  I think this is more a question for Staf first. The power routing inside the
  I/O pad is mainly defined by the I/O pad cells layout.

> the RTL8211 on the other hand, this can be given an External VREF for IO and it works
> fine at 3.3v.


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