[Libre-soc-dev] NGI POINTER gigabit ethernet router ASIC roadmap

lkcl luke.leighton at gmail.com
Thu Nov 4 23:55:30 GMT 2021

On November 4, 2021 10:22:46 AM UTC, lkcl <luke.leighton at gmail.com> wrote:

>otherwise, blocked delivery at the RS will ripple up the ready/valid
>signalling and a block at the output will cause a block at the input.

i have a working FSM, and a simple demo unit test based on test_inout_pipe.py.

performance utterly sucks, it introduces 4 extra cycles latency (!)  at least however it is functional.

it did however throw up a very interesting bug in MultiCompUnit where the write data "ok" handling requires to remain valid *after* results are produced (whoops).

setting write data + ok flag goes into wrmask combinatorially.

the only reason this bug hasn't been found before is that SimpleHandshake left data + ok set permanently with a m.d.sync

when i set the ReservationStation data plus "o_valid" for only one cycle, wrmask was not properly set.


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