[Libre-soc-dev] PLL integration

Jean-Paul Chaput Jean-Paul.Chaput at lip6.fr
Thu May 27 10:05:43 BST 2021

On Wed, 2021-05-26 at 20:43 +0100, Luke Kenneth Casson Leighton wrote:
> On Wed, May 26, 2021 at 8:29 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
> wrote:
> > 
> >   I confirm it is now fixed. Hope there is no other such things,
> >   as the P&R won't see them as errors.
> > 
> normally, we would run simulations to catch them - except this is a
> black-box.  and a pretty critical one.

  Ha. No, I was meaning "in the rest of the test issuer"...

  The PLL may be one of the most safe part of the chip. It has been
  completely simulated at spice level (and proved ok). And Dimitri has
  a long experience in those kind of design.

  Now that I also have manually and one by one checked the connexions
  I'm pretty confident that it is working.

> i'm tempted to suggest bypassing the PLL - still including it - but
> treating it entirely as a separate unit to which TestIssuer is **NOT**
> connected.

      .-.     J e a n - P a u l   C h a p u t  /  Administrateur Systeme
      /v\     Jean-Paul.Chaput at lip6.fr
    /(___)\   work: (33)              
     ^^ ^^    cell:   home:

    U P M C   Universite Pierre & Marie Curie
    L I P 6   Laboratoire d'Informatique de Paris VI
    S o C     System On Chip

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