[Libre-soc-dev] PLL integration
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu May 27 10:30:59 BST 2021
On Thu, May 27, 2021 at 10:05 AM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
> Ha. No, I was meaning "in the rest of the test issuer"...
> The PLL may be one of the most safe part of the chip. It has been
> completely simulated at spice level (and proved ok). And Dimitri has
> a long experience in those kind of design.
which is fantastic to hear
> Now that I also have manually and one by one checked the connexions
> I'm pretty confident that it is working.
ok, so what i mean is: testing its connections in simulation is tricky
(needing to use a VBE model not the actual SPICE in e.g. verilator
it's not Dimitri's work that is of concern, it's yosys handling of
i currently have this in the output from the build:
o Protect external components not useds as RoutingPads.
o Running global routing.
o Back annotate global routing graph.
[ 0] nets:[ERROR] Diskstra::load(): Net
"core.subckt_12347_test_issuer.ti_coresync_clk" do not have a driver.
which, oink, i'm reviewing the...
ahhh, the wrapped PLL has had the outputs all turned into inputs:
port ( clk_24_i : in bit
; clk_pll_o : in bit
; pll_test_o : in bit
; pll_vco_o : in bit
; clk_sel_i : in bit_vector(1 downto 0)
; vdd : linkage bit
; vss : linkage bit
this is despite the blackbox clearly saying they are outputs:
(* blackbox = 1 *)
module pll(ref , div_out_test, a0, a1, vco_test_ana, out);
input ref ;
and in the verilog (libresoc.v) they are clearly outputs:
(* \nmigen.hierarchy = "test_issuer.wrappll" *)
(* generator = "nMigen" *)
module wrappll(clk_24_i, pll_test_o, pll_vco_o, clk_sel_i, clk_pll_o);
input [1:0] clk_sel_i;
pll real_pll (
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