[Libre-soc-dev] PLL integration
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed May 26 20:43:51 BST 2021
On Wed, May 26, 2021 at 8:29 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
> I confirm it is now fixed. Hope there is no other such things,
> as the P&R won't see them as errors.
normally, we would run simulations to catch them - except this is a
black-box. and a pretty critical one.
i'm tempted to suggest bypassing the PLL - still including it - but
treating it entirely as a separate unit to which TestIssuer is **NOT**
instead the core is connected to the external sys_clk.
all PLL test signals still conected - just not the core to its output.
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