[Libre-soc-dev] PLL integration
Jean-Paul.Chaput at lip6.fr
Mon May 24 22:04:05 BST 2021
On Mon, 2021-05-24 at 21:46 +0100, Luke Kenneth Casson Leighton wrote:
> On Monday, May 24, 2021, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> wrote:
> > Yes... In my wrapper I did rename it automatically into "out_v".
> > I add "_v" to any VHDL keyword used as identifier.
> > I would prefer to keep, as much as possible, to stick to the original
> > names because they match the ones of the GDSII supplied by Dimitri.
> except, the name is "out" in the GDSII file.
Not a problem. I can rename it as I like. The GDSII file is never
used "directly". Is parsed inside Coriolis then used.
> therefore the wrapper creates the wrong name (v_out)
The wrapper I'm talking about is in the TSMC NDA covered that
you don't have. So, from where "v_out" do come from ?
There is an information I may be missing here.
> therefore it is impossible to join up the nets because there is no way to
> connect out_v to out.
.-. J e a n - P a u l C h a p u t / Administrateur Systeme
/v\ Jean-Paul.Chaput at lip6.fr
/(___)\ work: (33) 01.44.27.53.99
^^ ^^ cell: 06.66.25.35.55 home: 09.65.29.83.38
U P M C Universite Pierre & Marie Curie
L I P 6 Laboratoire d'Informatique de Paris VI
S o C System On Chip
More information about the Libre-soc-dev