[Libre-soc-dev] PLL integration
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon May 24 22:45:02 BST 2021
On Monday, May 24, 2021, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> wrote:
> > except, the name is "out" in the GDSII file.
> Not a problem. I can rename it as I like. The GDSII file is never
> used "directly". Is parsed inside Coriolis then used.
okaay. so there is sone parsing which substitutes "out" for "out_v"?
is it necessary then to change the pll.vbe and pll.v blackbox to use the
name "out_v"? (and also in the nmigen source)?
> > therefore the wrapper creates the wrong name (v_out)
> The wrapper I'm talking about is in the TSMC NDA covered that
> you don't have. So, from where "v_out" do come from ?
"fake" pll cell library with total rubbish inside it but the same netlist
it even works under "make cgt", it is possible to load and view the cell
i have created a similar one, library named LibreSOCMem and can load
spblock_512etcetc as well.
they both look like garbage but allow me to complete the P&R.
and, crucially, "follow along" with what you are doing under NDA.
There is an information I may be missing here.
with the "fake" cell i can do "import pll; pll.setup()"
and same for LibreSOCMem.
now i can create the blackboxes:
and P&R completes... or, it would... if only the pll had a signal named
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
More information about the Libre-soc-dev