[Libre-soc-dev] PLL integration
Jean-Paul.Chaput at lip6.fr
Mon May 24 21:42:15 BST 2021
Yes... In my wrapper I did rename it automatically into "out_v".
I add "_v" to any VHDL keyword used as identifier.
I would prefer to keep, as much as possible, to stick to the original
names because they match the ones of the GDSII supplied by Dimitri.
On Mon, 2021-05-24 at 20:50 +0100, Luke Kenneth Casson Leighton wrote:
> arrgh, the word "out" - a name of a signal in the PLL - is a VHDL keyword,
> isn't it?
> can we rename the signals in the GDS-II file to "pll_out", "pll_a0",
> "pll_a1" and so on?
> Libre-soc-dev mailing list
> Libre-soc-dev at lists.libre-soc.org
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