[Libre-soc-dev] PLL integration

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon May 24 20:50:41 BST 2021

arrgh, the word "out" - a name of a signal in the PLL - is a VHDL keyword,
isn't it?

can we rename the signals in the GDS-II file to "pll_out", "pll_a0",
"pll_a1" and so on?


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