[Libre-soc-dev] PLL integration

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat May 22 15:58:32 BST 2021

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On Sat, May 22, 2021 at 3:39 PM Marie-Minerve Louerat <
Marie-Minerve.Louerat at lip6.fr> wrote:

> Be aware that Dimitri, in the PLL has also used the standard cells of
> FlexLib, using the same names.
> I am a bit worried that on the main digital (LibreSoC), those cells are
> also used with possibly different details (since Dimitri may have made
> some minor but still, changes).

if it is inserting a "black box", full layout completed in GDS-II /
Alliance AP,
as a "unit", with the entire contents of that "black box" 100% full
and laid out already, then this should not be a problem at all.

if however that "black box" is *missing* the internals of the FlexLib cells
and it is expected that coriolis2 should substitute the contents of named
FlexLib cells *INTO* the PLL block, then that becomes an issue.

which one is it?


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