[Libre-soc-dev] PLL integration

Jean-Paul Chaput Jean-Paul.Chaput at lip6.fr
Sat May 22 21:59:37 BST 2021

On Sat, 2021-05-22 at 15:58 +0100, Luke Kenneth Casson Leighton wrote:
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> On Sat, May 22, 2021 at 3:39 PM Marie-Minerve Louerat <
> Marie-Minerve.Louerat at lip6.fr> wrote:
> > Be aware that Dimitri, in the PLL has also used the standard cells of
> > FlexLib, using the same names.
> > I am a bit worried that on the main digital (LibreSoC), those cells are
> > also used with possibly different details (since Dimitri may have made
> > some minor but still, changes).
> > 
> if it is inserting a "black box", full layout completed in GDS-II /
> Alliance AP,
> as a "unit", with the entire contents of that "black box" 100% full
> completed
> and laid out already, then this should not be a problem at all.
> if however that "black box" is *missing* the internals of the FlexLib cells
> and it is expected that coriolis2 should substitute the contents of named
> FlexLib cells *INTO* the PLL block, then that becomes an issue.
> which one is it?

  Already hit that particular %$#! bug... GDSII file is self contained,
  that is, it contains everything it needs, no external reference to
  other cells (like FlexLib).
    But it contains a *copy* of the cells used (like inv_x1 for example),
  so after loading into Coriolis, they will collides with the ones
  coming from FlexLib.
    To avoid that, Cells coming from a GDSII file will be prefixed by
  "gds_". So "inv_x1" will be renamed in "gds_inv_x1".
    This is far from foolproof and I need to design something more
  robust, but that will do for now.


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