[Libre-soc-dev] PLL integration
Marie-Minerve.Louerat at lip6.fr
Sat May 22 15:30:34 BST 2021
Be aware that Dimitri, in the PLL has also used the standard cells of
FlexLib, using the same names.
I am a bit worried that on the main digital (LibreSoC), those cells are
also used with possibly different details (since Dimitri may have made
some minor but still, changes).
For sure in the verification process, at least, it may be an issue (not
to mention the order of the terminals in the spice source netlist).
Le 22/05/2021 à 14:13, Luke Kenneth Casson Leighton a écrit :
> ok Jean-Paul i've got as far as i can (temporarily) get,
> i will need to create a (fake) PLL cell similar to the (fake) SRAM
> cell to get further.
> i have added functions to the (fake) FreePDK45 doDesign.py which
> search through the cell path names, you *DO NOT* need to manually
> name then rename then rename again then change yet again each
> and every laborious time.
> instead of subctk_NNNN_name1.subctk_MMMM_name2.subctk_OOO.subctk_PPPP
> the function will find exactly what you want, down each sub-component
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