[Libre-soc-dev] PLL integration

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat May 22 13:13:50 BST 2021

ok Jean-Paul i've got as far as i can (temporarily) get,
i will need to create a (fake) PLL cell similar to the (fake) SRAM
cell to get further.

i have added functions to the (fake) FreePDK45 doDesign.py which
search through the cell path names, you *DO NOT* need to manually
name then rename then rename again then change yet again each
and every laborious time.


instead of subctk_NNNN_name1.subctk_MMMM_name2.subctk_OOO.subctk_PPPP



the function will find exactly what you want, down each sub-component path.


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