[Libre-soc-dev] PLL integration
Jean-Paul.Chaput at lip6.fr
Sat May 22 12:12:59 BST 2021
On Sat, 2021-05-22 at 11:12 +0100, Luke Kenneth Casson Leighton wrote:
> On Sat, May 22, 2021 at 10:21 AM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
> > Hello Luke,
> > I am now in the final stage of the PLL integration and I am wondering
> > it it is correctly connected in the verilog I got. From what I can
> > guess "ref" goes straight to "out"
> and "a1" is hard-wired to "0".
From what I see, "a1" is connected to "clk_sel_i".
> a0 and a1 are the mux selection pins. if they are hardwired to zero then
> there is no way to control the internal operation and selection of
> frequencies by the divider.
OK. But now that I'm doing the final chip, I would need the true
connexions. I may correct myself the "libresoc.v" netlist.
* I/O pads for a0 & a1.
* "clk" of "ti" connected to "out" of PLL.
* "ref" of PLL connected to "clk" of "test_issuer".
(the existence of both "ti" and "test_issuer" component was a bit
misleading at first. I tend to confuse them).
.-. J e a n - P a u l C h a p u t / Administrateur Systeme
/v\ Jean-Paul.Chaput at lip6.fr
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