[Libre-soc-dev] PLL integration

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat May 22 12:33:02 BST 2021

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Sat, May 22, 2021 at 12:13 PM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>

> On Sat, 2021-05-22 at 11:12 +0100, Luke Kenneth Casson Leighton wrote:
> > On Sat, May 22, 2021 at 10:21 AM Jean-Paul Chaput <
> Jean-Paul.Chaput at lip6.fr>
> > wrote:
> >
> > >
> > > Hello Luke,
> > >
> > > I am now in the final stage of the PLL integration and I am wondering
> > > it it is correctly connected in the verilog I got. From what I can
> > > guess "ref" goes straight to "out"
> >
> >
> > yes.
> >
> > and "a1" is hard-wired to "0".
>   From what I see, "a1" is connected to "clk_sel_i".

please update.

> > a0 and a1 are the mux selection pins.  if they are hardwired to zero then
> > there is no way to control the internal operation and selection of
> > frequencies by the divider.
>   OK. But now that I'm doing the final chip, I would need the true
>   connexions. I may correct myself the "libresoc.v" netlist.

that would place you in the position of being an irrevocable and permanent
maintainer of an extremely large and complex auto-generated file, i do not
recommend it at all.

with the auto-generated output containing line numbers from the python
source - which change - and with litex failing to properly keep stable
names, any updating and merging would be an extreme nuisance.

>   * I/O pads for a0 & a1.
>   * "clk" of "ti" connected to "out" of PLL.
>   * "ref" of PLL connected to "clk" of "test_issuer".

please let me deal with it.  i have created a new "Instance" submodule, and
am restoring the original names so that Dimitry's PLL is wrapped inside
another module.

this ensures that the names of the signals which (had) been stable and
chosen for one year remain stable and do not change.

>   (the existence of both "ti" and "test_issuer" component was a bit
>    misleading at first. I tend to confuse them).

yeah it is between ti and test_issuer where the PLL is inserted.
test_issuer is the external name, containing the PLL, ti (test internal) is
the internal name which has the PLL connected to it.

* test_issuer code only runs at the incoming clk from the incoming sys_clk
* ti internal runs at the PLL clock


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