[Libre-soc-dev] PLL integration

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat May 22 12:03:56 BST 2021

On Sat, May 22, 2021 at 11:12 AM Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> a0 and a1 are the mux selection pins.  if they are hardwired to zero then
> there is no way to control the internal operation and selection of
> frequencies by the divider.
ok try this

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