[Libre-soc-dev] PLL integration

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sat May 22 11:12:06 BST 2021

On Sat, May 22, 2021 at 10:21 AM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>

> Hello Luke,
> I am now in the final stage of the PLL integration and I am wondering
> it it is correctly connected in the verilog I got. From what I can
> guess "ref" goes straight to "out"


and "a1" is hard-wired to "0".

a0 and a1 are the mux selection pins.  if they are hardwired to zero then
there is no way to control the internal operation and selection of
frequencies by the divider.


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