[Libre-soc-dev] PLL integration

Jean-Paul Chaput Jean-Paul.Chaput at lip6.fr
Sat May 22 10:21:46 BST 2021

Hello Luke,

I am now in the final stage of the PLL integration and I am wondering
it it is correctly connected in the verilog I got. From what I can
guess "ref" goes straight to "out" and "a1" is hard-wired to "0".

I am on commit 3168ed1 of soclayout (after 5faa53a).


      .-.     J e a n - P a u l   C h a p u t  /  Administrateur Systeme
      /v\     Jean-Paul.Chaput at lip6.fr
    /(___)\   work: (33)              
     ^^ ^^    cell:   home:

    U P M C   Universite Pierre & Marie Curie
    L I P 6   Laboratoire d'Informatique de Paris VI
    S o C     System On Chip

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