[Libre-soc-dev] VERSA_ECP5 JTAG TAP interface confirmed functional
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Apr 15 19:47:33 BST 2021
(please do trim context, tobias)
On Thu, Apr 15, 2021 at 6:40 PM Tobias Platen
<libre-soc at platen-software.de> wrote:
> > overall these comprehensive tests gives us confidence that the ASIC
> > will at least be functional in some fashion, and keep us from
> > introducing errors at each stage, from HDL, to FPGA, to layout as an
> > actual ASIC.
> > l.
> That looks great. I already had a look at the ULX3S which has 32 MB
> SDRAM. I doubt that this is enough for booting Linux.
it's barely enough for something like openwrt, which is specifically
designed for 8MB and 16MB boards.
More information about the Libre-soc-dev