[Libre-soc-dev] VERSA_ECP5 JTAG TAP interface confirmed functional

Tobias Platen libre-soc at platen-software.de
Thu Apr 15 18:40:32 BST 2021

On Thu, 2021-04-15 at 16:27 +0100, Luke Kenneth Casson Leighton wrote:
> i completed the test of the c4m-jtag TAP interface today using an
> FT232 usb device from DCD Tech.  that's "actual JTAG implemented
> entirely in nmigen" not "the ECP5's own JTAG port which is only
> accessible via an undocumented series of shift registers".  (here is
> some links to how that undocumented interface access is done in
> verilog):
> https://bugs.libre-soc.org/show_bug.cgi?id=498
> we are instead *actually* implementing *actual* JTAG TAP in Libre-SOC
> using Chips4Makers c4m-jtag HDL, written in nmigen:
> https://git.libre-soc.org/?p=c4m-jtag.git;a=blob;f=c4m/nmigen/jtag/tap.py;hb=HEAD
> connecting up in litex was done by specifying an io extension (with
> thanks to daveshah on how to do that):
> https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=versa_ecp5.py;h=487c96bda45ead1ce313cdd6a05928f5304f02f1;hb=702b90659170e59af9452b409fce89c87fbbd239#l44
> where litex imports the LibreSOC lnstance and provides the 4 JTAG
> signals here:
> https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=libresoc/core.py;h=8fae4198f7ba4b7e526a4a8c99a3c834b4efc30e;hb=702b90659170e59af9452b409fce89c87fbbd239#l254
> the Chips4Makers JTAG TAP instance is declared here:
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/jtag.py;h=ea15b31f9d040b7353c0e71fd5e89e8b21576599;hb=4970606fa9b5cfe2de748850c37875c4816f4b75#l64
> and its default behaviour is to create an idcode with a manufacturing
> id of 0x18ff.  we then add a full boundary scan of all litex
> peripherals (SDRAM, UART, I2C, SPI, GPIO), a wishbone master so as to
> be able to access the full memory bus and also memory-mapped
> peripherals and associated CSRs, and a DMI interface that conforms to
> that used by Microwatt.
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/dmi.py;hb=HEAD
> the DMI interface allows the OpenPOWER registers to be read, and also
> allows it to be stopped, single stepped, and reset.  a simple
> "firmware uploader" program was written which can be used to program
> a
> LibreSOC core fully over JTAG:
> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/debug/firmware_upload.py;hb=HEAD
> this program uses OpenOCD "remote interface" protocol (bitbanging
> over
> TCP socket) so if openocd is connected back-to-back with a live ECP5
> FPGA the firmware_upload.py program can reset it, pause it, send a
> program into memory over JTAG, and set it running then monitor
> progress.
> [the exact same firmware upload program has also been successfully
> run
> against the litex sim.py (verilator simulation): this was enabled
> through modifying litex to enable the jtagremote module].
> also of potential interest is that we are also doing pre- and post-
> layout simulation of Libre-SOC using cocotb to access the exact same
> (simulated) JTAG TAP interface:
> https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=tree;f=ls180;hb=HEAD
> this includes a boundary scan, as well as the ability to read and run
> a SVF file:
> https://git.libre-soc.org/?p=soc-cocotb-sim.git;a=blob;f=ls180/pre_pnr/test.py;hb=HEAD
> the idea here is that when the ASIC comes back from IMEC TSMC 180nm,
> the exact same tests as above can be run, by either running the exact
> same SVF files through openocd, or by using an FT232-to-remote-
> bitbang
> adapter and running the same firmware_upload.py script, this time
> against the actual ASIC rather than an FPGA or a simulation.
> overall these comprehensive tests gives us confidence that the ASIC
> will at least be functional in some fashion, and keep us from
> introducing errors at each stage, from HDL, to FPGA, to layout as an
> actual ASIC.
> l.
That looks great. I already had a look at the ULX3S which has 32 MB
SDRAM. I doubt that this is enough for booting Linux. There are two
other ECP5 dev boards, the LogicBone [1] and the Akita [2]. [1] has
more RAM, but it seems to use a smaller FPGA.

[1] https://github.com/oskirby/logicbone
[2] https://hackaday.io/project/165036-akita

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