[Libre-soc-dev] daily kan-ban update 22sep2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue Sep 22 20:58:47 BST 2020
On Tue, Sep 22, 2020 at 8:15 PM Tobias Platen
<libre-soc at platen-software.de> wrote:
> Today: reading ls180.py versa_ecp5.py and ls180soc.py after no activity for some time
these basically define the pinouts (ls180.py) and the peripherals
(ls180soc.py) for the 180nm ASIC. versa_ecp5.py is for building
libresoc to run on a VERSA ECP5 FPGA developer board from Lattice
Semi. the other relevant one is "sim.py" which just runs libresoc or
microwatt through verilator and a simulated suite of peripherals.
oh i got JTAG running (in sim.py) by using the litex "jtagremote"
module, i was amazed that it worked after connecting openocd to it.
the only problem being: there's not one single powerpc processor
defined in openocd! wark-wark.
i will look tomorrow at the c4m jtag-svf code to see if it can be
adapted to "talk" to openocd-compliant network devices.
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