[Libre-soc-dev] daily kan-ban update 22sep2020

Tobias Platen libre-soc at platen-software.de
Tue Sep 22 20:15:37 BST 2020

Today: reading ls180.py versa_ecp5.py and ls180soc.py after no activity for some time

On Tue, 22 Sep 2020 12:16:28 +0100
Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:

> bit of a stressful scary moment on discovering that there's a bug in
> the divwe, divde, divweu and divdeu pseudocode for the simulator.  the
> overflow conditions for divwe are "result must fit completely in lower
> 32 bits" and of course the test was, thank you IBM MSB0 / LSB0,
> testing the wrong half of the intermediate result.
> 2 days before a code-freeze, thank god it was just the simulator not the HDL.
> ngggggh!
> i am back to adding JTAG to ls180soc, should be very straightforward.
> l.
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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Tobias Platen <libre-soc[at]platen-software[dot]de>

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