[Libre-soc-dev] Libre-SOC Versa ECP5 FPGA, Litex BIOS first boot

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Sep 3 17:46:11 BST 2020

On Thursday, September 3, 2020, Jacob Lifshay <programmerjake at gmail.com>

> > with many thanks to everyone who's helped make this happen, we have a
> > successful bring-up of the Litex BIOS including initialisation of the
> > DDR3 DRAM on the ECP5 FPGA.  how it managed to run at all under litex
> > sim.py at all, last month, will remain a mystery.
> >
> Yay!

about time :)

> You really should use a screen capture program -- none of the text on
> screen in the video was possible to read even when set to the highest
> resolution

ironically the capture would be identical to the sim.py run a few weeks ago.

the reason for the video is to show the FPGA board behind the laptop.
screen capture can't include that. (doh)


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

More information about the Libre-soc-dev mailing list