[Libre-soc-dev] Libre-SOC Versa ECP5 FPGA, Litex BIOS first boot
programmerjake at gmail.com
Thu Sep 3 16:21:15 BST 2020
On Thu, Sep 3, 2020, 03:36 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> with many thanks to everyone who's helped make this happen, we have a
> successful bring-up of the Litex BIOS including initialisation of the
> DDR3 DRAM on the ECP5 FPGA. how it managed to run at all under litex
> sim.py at all, last month, will remain a mystery.
You really should use a screen capture program -- none of the text on
screen in the video was possible to read even when set to the highest
the primary reason i think why it worked was simply that i'd fixed a
> ton of instruction issues through the side-by-side checking against
> microwatt. i've done 1.bin, 2.bin and 3.bin by hand, there, and
> they're all ok as best can be determined.
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