[Libre-soc-dev] Libre-SOC Versa ECP5 FPGA, Litex BIOS first boot

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Sep 3 11:35:43 BST 2020


with many thanks to everyone who's helped make this happen, we have a
successful bring-up of the Litex BIOS including initialisation of the
DDR3 DRAM on the ECP5 FPGA.  how it managed to run at all under litex
sim.py at all, last month, will remain a mystery.

the primary reason i think why it worked was simply that i'd fixed a
ton of instruction issues through the side-by-side checking against
microwatt.  i've done 1.bin, 2.bin and 3.bin by hand, there, and
they're all ok as best can be determined.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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